1. Field of the Invention
The present invention relates to an oscillator circuit. More specifically, the present invention discloses an efficient CMOS oscillator, which effectively doubles the frequency of a single-ended input signal.
2. Description of the Prior Art
The need for higher frequency reference signals has exacerbated the importance of frequency multiplication circuits that preserve phase noise at an affordable cost.
While Phase Locked Loops (PLL) are widely used, a PLL's phase noise performance is mainly limited to that of its voltage control oscillator (VCO). For phase noise and jitter sensitive applications, non-PLL frequency multiplication is required, in particular frequency doublers.
One type of frequency doubler uses a mixer to derive the higher frequency and filter out the subharmonics and undesired harmonics. However, these solutions only achieve limited harmonic and subharmonic rejection.
Other disadvantages to conventional approaches are designs that only exist in Bipolar (BJT and HBT) transistors and are not available in CMOS technology.
Furthermore, conventional low-cost techniques are unavailable for efficiently utilizing a single-ended input signal as a reference frequency source.
Therefore, there is need for a CMOS oscillator circuit, which effectively doubles the frequency of a single-ended input signal and exhibits improved subharmonic rejection and low phase noise.